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SRC/SEMATECH Engineering Research Center for Environmentally Benign Semiconductor Manufacturing |
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Transistor in 2005
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Gate oxide thickness < 1 nm Channel Length < 50 nm Junction depth < 50 nm Size of an atom ~ 0.5 nm
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The goal of Thrust B is to develop innovative processes that dramatically reduce water, chemical and energy use, and the waste generated by front-end-of-line manufacturing of the transistor gate stack. Project areas include gas phase and densified fluid wafer cleaning, selective atomic-layer deposition and plasma etching of high-k materials, and process flow alternatives for new device structures.
ERC researchers at Stanford University, the University of Arizona, and the University
of California-Berkeley (list below) are
currently working on the following research areas:
[UPDATE IN PROGRESS]
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