Table of ContentsGas Phase Cleaning of Semiconductor Wafer Surfaces Payoffs from Gas Phase Wafer Cleaning Technology 40°C SiO2 Etching Rate Response Surface Definition of Silicon Dioxide Etching Regimes Conclusions from HF/vapor SiO2 Etching Study Joint Project on Gas Phase Cleaning Processes University of Arizona/Stanford |
Author: Anthony J. Muscat
Email: ajmuscat@email.sjsu.eduu Other information: |