Gate Structure / Measurement Setup
p-Si (p+)
Silicate/SiO2 (~1.5 nm)
p-epi (2.75 um)
ZrO2 (~5 nm)
Al/TiN Electrode
(~200 nm)
±Vg
Test Structure
Dielectric Deposition
ALD by ASM Microchemistry
Precursors : ZrCl4, H2O
Temperature : 300 oC
Test Conditions
C-V : HP 4284A
I-V : HP 4140B
Test temperature : 25 oC
Voltage step : 0.05 V
Delay Time : 1 sec
Cap Area = 7.225x10-5 cm2
Substrate Material
Minimize series resistance
p-epi (NA ~ 1x1016 cm-3)
p-sub (NA ~ 1x1019 cm-3)
700 oC NH3 RTN
Al backside contact
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