PPT Slide
NSF/SRC
Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
Trench Device Fabrication
Fabrication on 6” wafer by HP
Mentor: Russ Parker
Engineers: Shawming and Melody Ma
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Deposit 0.5 mm TEOS SiO2
Deposit 0.2 mm poly-Si
Remove from backside
Poly-Si patterning
Poly-Si etch
Resist removal
Poly-Si dopant implant
and activation
Deposit 3 mm TEOS SiO2
Contact pad patterning
Pad area SiO2 etch
Resist removal
Trench patterning
Trench oxide etch
Trench poly-Si etch
Trench oxide etch
Resist removal
Mask 1
Mask 2
Mask 3
Photoresist
Poly-Si
TEOS SiO2
Si substrate
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