SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing (ERC)

                                                          **  Bringing Sustainability to Semiconductor Manufacturing **

A multi-university research center leading the way to environmentally friendly semiconductor manufacturing, sponsored by the Semiconductor Research Corporation's Global Research Collaboration (GRC) Research Program



Home  : Seminar Series : Schedule

Adobe Acrobat Reader For archived presentations:  1998  1999   2000  2001  2002  2004

- 2003 -
Jan. 2, 2003 NO TeleSeminar--HAPPY NEW YEAR!
Jan. 9 Host:  Karen Gleason, Massachusetts Institute of Technology
Presentation guest:  Dr. Ebrahim Andideh, Director of Polymer Memory Technology Development, Intel Corp. (Hillsboro, OR)
Topic: Evaluation and Evolution of ILD Materials and Integration Schemes"
With the reduction of integrated circuit dimensions and increase in microprocessor speed, the associated increase in interconnect RC time delays and power consumption become performance-limiting factors.  Interlayer dielectrics (ILD) for the next processor generation must therefore possess lower dielectric constants. Currently, fluorinated silica glasses (SiOF) are widely used as ILD, with k values in the range of 3.5 to 3.8. The goal will be to decrease this to k < 3.0 for the next generation of microprocessors.
A variety of materials have been explored as low k dielectrics, including polyarylenes, fluoro-organic polymers, and carbon doped oxides (CDOs).  The latter class indicates materials that are organosilicate glasses, where the organic functions in the film are groups bound to silicon (such as Si-CH3). CDO films can be obtained by CVD or spin-on methods, and have been generated in porous or non-porous forms. In the case of SiOF, the exchange of the less polar Si-F function for Si-O in the glass is responsible for the decreased dielectric constant; a similar effect occurs due to the presence of Si-C bonds in CDO. The lower film densities, especially for porous materials, also contribute to a decrease in k value. 
This presentation will include the challenges for the low k materials integration.  Detail evaluation and screening of the new low k materials is delineated to accelerate the learning.  Many aspects of these materials and the deciding factors for selection and possible integration schemes for each class of low k materials are discussed.
We will present data on material properties such as hardness/modulus, adhesion/cohesion, cracking thickness threshold, patterning interaction, etch selectivity, CMP defects, and impact of different process steps on k value.  There is a correlation between k value and thermal-mechanical properties of CDO. 
We have integrated Cu and CDO in a multi-layer Cu dual damascene structure with line-to-line leakage current matching that of FSG.   Improvement in line-to-line effective k of greater than 20% has been achieved. (PDF)
Jan. 16 Host:  David Graves, University of California-Berkeley
Presentation by: 
Matthew Radtke and David Graves, UC-Berkeley
"Evaluation of ESH Impact for Plasma Etch: Etch By-Products"
The ITRS has identified a "need for an integrated way to evaluate and quantify ESH impact of process, chemicals, and process equipment, and to make ESH a design parameter in development procedures for new equipment and processes." One targeted area is plasma etch for new materials. The ITRS notes that early identification of ESH impacts is crucial for simultaneous selection of processes and chemicals and minimizing ESH impacts. Plasma etching is especially challenging in this regard since the plasma often scrambles the incoming gases and etched materials to form completely new compounds. The first step in assessing the potential ESH impacts of these new compounds is to develop a methodology to identify their nature, source and transport.
We report initial results in characterizing plasma etch by-products for various materials and etch gases. After establishing the methodology with a fairly well understood system (Si etch in Cl2/O2 plasmas), we examine etch by-products for a possible new gate electrode material: RuO2. Concern has been expressed that the possibly toxic RuO4 will form during etch of this material. We have established clear evidence for the importance of etch product ionization and surface re-deposition within the chamber. In the case of RuO2 etching in O2 plasmas, no evidence was observed for volatile RuO4 formation and transport to the exhaust. However, the importance of chamber surface (and wafer) re-deposition from ionized etch products suggests that wall material and chamber cleaning will be major potential ESH concerns, depending on the composition of these deposits and their subsequent reactions during chamber cleaning. (PDF)
Jan. 23 Host:  Srini Raghavan, University of Arizona
Presentation by: 
James Farrell, Associate Professor, Department of Chemical and Environmental Engineering, University of Arizona
Topic:  "Electrochemical Treatment of Wastewaters Containing Organic Compounds"
In recent years there has been growing interest in developing destructive treatment methods for removing organic contaminants from wastewater streams and drinking water supplies.  This talk will discuss electrochemical methods for treating wastewaters containing chlorinated organic compounds, low molecular weight alcohols, and organic chelating agents.  Topics to be addressed include: 1) the limitations on electrochemical methods imposed by the Nernst and Butler-Volmer equations; 2) the importance of direct and indirect reduction and oxidation mechanisms; 3) the choice of electrode materials; 4) the trade-off between reaction rates and Faradaic current efficiencies; and 5) electrode fouling and degradation. 
Jan. 30 No TeleSeminar
Feb. 6 No TeleSeminar -- ERC Annual Review Meeting -- Tucson, AZ
Feb. 13 No TeleSeminar
Feb. 20 Host:  Duane Boning, Massachusetts Institute of Technology
Presentation by:  Dr. Tae Park, Massachusetts Institute of Technology
"Chip-Scale Modeling of Copper Plating Pattern Dependencies"
Abstract:  Copper metallization has emerged as the leading interconnect technology for deep sub-micron features, where electroplating and chemical mechanical polish (CMP) processes have a vital role in the fabrication of integrated circuits. The processes both suffer from a similar problem: the copper electroplated profiles and the polished surface exhibit pattern dependent topography. In this talk, a methodology for the characterization and modeling of pattern dependent problems in copper interconnect topography is described. For the electroplating process, the methodology consists of test structure and mask design to examine feature scale copper step height and the height of copper array regions as a function of underlying layout parameters. Semi-empirical response surface models are then generated with model parameters extracted from conventional and superfill plating processes. Once the models are calibrated, layout parameters including pattern density, line width distributions, and line length are extracted for each cell in a 40 mm by 40 mm discretization of any random chip layout. Then, a chip-scale prediction is achieved by simulating generalized average heights for each grid cell across the entire chip. The prediction result shows root mean square errors of less than 1000 A for array height and around 500 A for step height. This methodology provides the first known chip-scale prediction of electroplated topography. (PDF)
Feb. 27 Host:  Anthony Muscat, University of Arizona
Presentation by:  Andrew E. Feiring, DuPont Central Research & Development, Experimental Station 
Topic:  "Design of Transparent Fluoropolymers for Semiconductor Manufacture at 157 nm"
AbstractPhotolithography at 157 nm for new generations of semiconductor manufacture requires new photoresists which are highly transparent at the imaging wavelength.  We have developed highly transparent partially fluorinated polymers with the functionality for  chemically amplified imaging and aqueous development.  Leading candidates include  terpolymers of tetrafluoroethylene (TFE), hexafluoroisopropanol-substituted norbornenes and tertiary alkyl acrylates.  The polymers are prepared in solution using a semibatch process which must be carefully controlled due to the widely varying monomer reactivity ratios.  Polymer synthesis on multi-kilogram scale has been demonstrated and fully formulated resists have been imaged in a 157 nm microstepper.  Polymer properties may be further enhanced by replacing the norbornene group by appropriately substituted, partially fluorinated tricyclononenes.  In contrast, novel TFE/"bulky" vinyl ether copolymers, which have suitably high glass transition temperatures and good etch resistance, have surprisingly high absorbance at 157 nm making them unsuitable for this application.   Blending studies have been done on polymers containing hexafluoroisopropanol groups which are critical components in these polymers. (PDF)
March 6 Host:  Charles Musgrave, Stanford University
Presentation by:  Joseph Han, Stanford University
Topic: "Understanding Atomic Layer Deposition of ZrO2 and HfO2 Using Density Functional Theory" 
Abstract: In order to maintain the scaling predicted by Moore’s Law, the gate length in complementary metal-oxide-semiconductor (CMOS) transistors has been shrinking for the past 25 years.  Accompanying this decrease in gate length is the requirement that the gate thickness decrease to maintain sufficient field strength in the channel region.  Traditionally, silicon oxide (SiO2) has been used for the gate oxide because of its ideal mechanical, electrical, and interfacial properties with the silicon substrate; however, current technologies require sub-0.1 μm thickness.  At these dimensions, electrons tunnel through the gate causing additional leakage current which introduces significant problems such as poor power efficiency and excessive heat.  By introducing high-κ materials into the gate stack, the thickness can be increased to minimize tunneling.  Two proposed materials are zirconia (ZrO2) and hafnia (HfO2) which have dielectric constants an order of magnitude greater than that of SiO2.  Furthermore, the thickness of the gate must be controlled precisely.  Atomic layer deposition (ALD), where the substrate is exposed to alternating precursors that have self-limiting reactions on the surface, is ideal because of the ability for precise thickness control by counting the number of exposure cycles.
In this study we have used density function theory (DFT) to explore the energetics of ALD of ZrO2 and HfO2.  We find that the metal-chloride precursors, ZrCl4 and HfCl4, exhibit trapped intermediate states with the reactions being endothermic compared to the initial adsorbed state.  By increasing the temperature, the equilibrium can be shifted towards the product; however, at these temperatures, desorption is favored over reaction.  These characteristics could explain the sub-monolayer growth rates seen experimentally.  Recently, there has been interest in alternative precursors such as alkylamides.  Our calculations for ALD reactions with Hf(N(CH3)2)4 show that this precursor does not exhibit the strong trapped intermediate state and that the overall reaction is exothermic.  As such, the alkylamide precursor should have improved growth rates as compared with the chloride precursors which has been seen experimentally.  The trapped states are weakened compared to the chloride precursors because the electronic structure is such that there are few stable unoccupied orbitals that can be used to form the complex.  The exothermic nature of the alkylamide precursor is due to the relative strengths of the bonds being broken and formed.  With this information, we can now suggest and evaluate new precursors that can lead to improved ALD reactions for ZrO2 and HfO2. (PDF)
March 13 Host:  Kimberly Ogden, University of Arizona
Presentation by:  Kim Ogden and Arturo Ruiz-Yeomans, University of Arizona
Topic:  (Ogden) "Minimizing the Number of Quick Dump Rinse Cycles in Etch and Resist Strip Wet Benches"
(Ruiz-Yeomans) "Biotreatment of Organic Compounds and Copper in Waste Streams from Semiconductor Manufacturing"
Abstract (Ogden): One of the goals of the Silicon Technology Roadmap is to reduce water usage by 20% by 2004. To achieve this goal all wet processing must be evaluated with regards to rinse efficiency. This presentation addresses minimizing the number of Quick Dump Rinse (QDR) cycles for Buffered Etch Oxide (BOE) processes and positive resist removal processes.  For BOE processes, it was found that pH is an excellent initial indicator to determine the number of QDR cycles to remove BOE from the wafer surfaces. More precise data was obtained using an ion chromatograph, and the amount of carry-over fluorine was correlated with the number of wafers. Temperature was the most significant factor that influenced removal of fluorine from wafer and cassette surfaces. The lower the temperature the faster the fluorine is removed from the wafer surface and the less adhesion of contaminant particles to wafer surfaces. For positive resist strip processes, the minimum number of QDR cycles was determined by analyzing the water for residual carbon. (Kimberly Ogden, Jay Barber [Texas Instruments, Tucson] and Elizabeth Swanson [UA]) (PDF)
Abstract (Ruiz-Yeomans): The main objective of this project is to study the viability of biotreatment as a wastewater treatment technique applicable to the semiconductor industry. Previously this project has focused in developing and studying techniques to treat waste streams that contain either organic compounds or copper.
This presentation focuses in the development of treatment strategies to simultaneously treat waste streams containing both organics and copper. Two different configurations of bioreactors are tested. A one-stage bioreactor that treats both copper and IPA as our model organic, and a two-stage bioreactor consisting of a copper-treating bioreactor followed by an IPA-treating bioreactor. 
The one-stage bioreactor system was found to treat copper effectively but did not have the same efficiency at treating IPA. The two-stage bioreactor was able to treat both copper and IPA effectively and had the advantage of allowing for independent optimization of each of the two-stages. (Arturo Ruiz-Yeomans and Kimberly Ogden, University of Arizona) (PDF)
March 20 Host:  Farhang Shadman, University of Arizona
Presentation guest:  Professor Masud Mansuripur, Optical Sciences Center, University of Arizona
Topic:  "Information Storage and Retrieval using Macromolecules as Storage Media"
To store information at extremely high-density and data-rate, we propose to adapt, integrate, and extend the techniques developed by chemists and molecular biologists for the purpose of manipulating biological and other macromolecules. In principle, volumetric densities in excess of 1021 bits/cm3 can be achieved when individual molecules with dimensions below a nanometer or so are used to encode the "0's" and "1's" of a binary string of data. In practice, however, given the limitations of electron-beam lithography, thin film deposition and patterning technologies, molecular manipulation within submicron dimensions, etc., we believe that volumetric storage densities on the order of 1016 bits/cm3 (i.e., petabytes per cubic centimeter) should be readily attainable, leaving plenty of room for future growth. The unique feature of the proposed new approach is its focus on the feasibility of storing bits of information in individual molecules, each only a few angstroms in size. Nature provides proof of principle for this type of data storage through the ubiquitous existence of DNA and RNA molecules, which encode the blueprint of life in four nucleic acids: Adenine, Guanine, Cytosine, and Thymine/Uracil. These macromolecules are created on an individual basis by enzymes and protein-based machinery of biological cells, are stable over a fairly wide range of temperatures, are read and decoded by ribosomes (for the purpose of manufacturing proteins), and can be readily copied and stored under normal conditions. Advances in molecular biology over the past decades have made it possible to create (i.e., write) artificial molecules of arbitrary base-sequences, and also to decode (i.e., read) such sequences. These techniques can now be adapted and extended in the service of a new generation of ultra-high-density data storage devices. Macromolecular strings (representing blocks of data several megabytes long) can be created on-demand, then stored in secure locations (i.e., parking spots) on a chip. These data blocks can then be retrieved by physically moving them to decoding stations (also located on the same chip), subjecting them to a "read" process, then returning them to their secure parking spots until the next request for readout is issued, or until there is a call for their removal and destruction (i.e., erasure). (PDF)
March 27 Host:  Anthony Muscat, University of Arizona 
Presentation guest:  Holly Ho, International SEMATECH
"A Review of Life Cycle Assessment Data Availability"
Abstract:  There is interest by the semiconductor industry to use gate-to-gate life cycle analysis (LCA) as a tool to compare the environmental impact of alternative processes and chemicals used in manufacturing and to identify the manufacturing steps that create the greatest impact.  In some cases even a full LCA is being considered to determine what phase of a product’s life cycle --- raw materials extraction, product manufacture, product use, or end-of-life disposal --- results in the greatest environmental impact.  From some preliminary work by International SEMATECH and others, there is an indication that existing databases are very limited in the information that they contain for the chemicals typically used in the semiconductor industry.  To assess this potential deficiency in more depth, International SEMATECH initiated a project in 2002 on LCA. 
International SEMATECH identified six representative chemicals used in semiconductor manufacturing.  These were selected from a more extensive “Top 20” list assembled based on selection criteria, which included the “quantity used”, “health and safety considerations”, and “environmental concerns such as global warming”.  The six chemicals finally chosen were NMP, HMDS, TMAH, NF3, Ethyl Lactate and Sulfuric Acid.

This study explored eight of the most extensive and widely used databases.  The review included the “production inventory” (environmental aspects and/or impacts resulting from manufacturing the chemical) and “material impacts” (impacts resulting from the chemical itself if freely present in the environment). Both are quantified per unit mass of the chemical.  In this study production inventory data were located only for sulfuric acid, while at least some, albeit very little, material impact data was found for four of the six chemicals.  It was concluded that currently available databases contain only data for commonly used materials or for specialty or “niche” chemicals known to be associated with specific environmental concerns.  As part of this study a five-step methodology was developed to deal with this data gap.  This methodology and study results will be described in more detail in this presentation. (Holly Ho* and Walter F. Worth) (PDF)
April 3 Host:  Christopher Ober, Cornell University
Presentation by:  James B. McClain, Ph.D., President and CTO of Micell Technologies and Micell Integrated Systems, Raleigh, N.C. 
and Peter Nguyen, Cornell University
TopicMcClain:  "Microelectronic Device Manufacturing with CO2"
Topic:  Nguyen:  "Using scCO2 and Cosolvents for Microelectronics Processing"
Abstract:  McClain:
Carbon dioxide, the same substance that puts the bubbles in champagne and is used in the freeze-drying of food, when compressed into a liquid or supercritical fluid has great utility as a performance-enabling and sustainable process solvent in applications including chemical processing, surface and polymer science and engineering practice.  Micell Technologies (, founded in 1996 on supercritical CO2-based technology discovered at UNC-Chapel Hill, for has built a platform of product innovation and commercialization that ranges from retail dry cleaning to semiconductor cleaning and high performance surface modification processes.  In this discussion we will focus on the application of supercritical CO2 to the cleaning and surface modification of semiconductor materials in fabrication.  An integrated formulations-chemistry, process engineering and apparatus approach has demonstrated ¾ results including: 
·        Drying of nano-scale structures in a single-step incorporation of water into scCO2.  Performance of a chemically-modified scCO2 formulation has been demonstrated on drying of high aspect ratio lithographic images and on removal of surface absorbed water on and in dielectric materials.  
·        Repair of the surface of SiOx-based dielectric materials that have been degraded by etch processes.  Formulations of active chemistry, delivered through scCO2 repairs the degradation of dielectric by formation of SiOH groups during etch.  
·        Removal of post-etch hardened photoresist residues and post-ash residues from via structures on low-k dielectric materials.  An integrated chemical formulation including active chemistries, surfactants and co-solvents has been coupled to process and fluid modeling to provide cleaning results at very rapid cycle times.  
·        Removal of metallic residues from semiconductor substrates.  Results have been generated for the surface removal and entrainment of copper and other ions in scCO2 cleaning (notable for removal of back-sputtered copper in the post barrier-breakthrough step of the dual damascene process). ·        Process methodologies to enable rapid throughput, filling, draining and chemical formulation management on extremely delicate surface structures (MEMS application).   
·        SEMI compatible alpha-chamber processing 200mm wafers in either stand-alone or cluster-tool configuration.   

These technologies as well as applications of scCO2 in pattern transfer and barrier/seed layer deposition are the primary focus areas of Micell in semiconductor processes.  The company is structured to deliver these technologies to leading OEMs and End-users through partnerships and joint product development relationships. (PDF)

Abstract:  Nguyen
Modern advances in integrated circuit (IC) technology have presented many complex issues ranging from practical to environmental.  The increased use of organic solvents, halogenated solvents, and water in manufacturing and processing of ICs has led to a need for environmentally responsible and energy efficient alternatives. Possibilities include liquid and supercritical carbon dioxide (scCO2.)  Using CO2 can be advantageous because CO2 has a number of benefits.  For example, CO2 is inexpensive, nonflammable, environmentally benign, and can be completely and easily removed from other products.  In addition, scCO2 is not hindered by surface tension and can operate under reasonable conditions.  Despite having a somewhat limited solvating ability, it has been well established that by adding a small volume of polar solvents (also called co-solvents, modifying solvents, or modifiers) to an scCO2 mixture, the solubility of a polar solute in scCO2 can dramatically increase.  This fact makes scCO2 technology extremely attractive as an alternative solvent.  We show that scCO2 can be used with a variety of cosolvents as an alternative solvent to traditional organic solvents in order to develop a number of next-generation negative-tone photoresists as well as some of the considerations for using such technology. (PDF)
April 10 Host:  Krishna Saraswat, Stanford University
Presentation by:  Rong Chen (Chemistry) and Hyoungsub Kim (Materials Science and Engineering), Stanford University
Topic: "Surface Modification for Area-Selective Atomic Layer Deposition”
Gate dielectrics with permitivities greater than that of SiO2-based materials are required to continue downward dimensional scaling of MOSFET devices. However, introduction of new metal-oxide based dielectrics in future transistors introduces a host of difficult challenges associated with film deposition, interface stability, electrical performance and reliability. There is a need for novel gate dielectric processing methods and an understanding of how synthesis method affects the structure and properties of high-k dielectric layer. Among many possible deposition techniques for preparing ultra-thin metal oxide films, atomic layer deposition (ALD) is very promising because it can produce high quality films essentially perfect conformality and precise film thickness control.  It occurs through a sequence of self-limiting surface reaction steps which may result in film deposition one monolayer at a time. While ALD inherently provides nano-scale control of materials in the vertical direction, the area-selective ALD technique will enable nano-scale definition of the lateral structure as well. Availability of area-selective ALD processes for gate dielectric and gate electrode deposition could substantially reduce the number of lithography mask-steps, etch, and cleaning operations required for integrate circuit fabrication.
In the presentation, we will show our latest experimental results that emphasizes controlling the substrate surface chemistry in order to impart selectivity to ALD. By area-selective ALD, we mean deposition of an inorganic film onto a patterned substrate in which certain well-defined regions have been “primed” for deposition and others have been “deactivated.” We focus on HfO2 as the high-k gate dielectric layer for ALD process. Preliminary failure of gas phase delivery of small deactivate agents have been introduced as the motivation for longer chain alkylhalosilanes. Octadecyltrichlorosilane (ODTS) is a well known self-assembled monolayers (SAMs) for a few decades. Well-ordered condensed ODTS monolayer can effectively block HfO2 growth on top through ALD process, which is very promising for both micro-contact printing and directly patterning through UV, electron beam lithography or scanning probe writing.  Finally, we also show that condensed shorter length films show better blockage effect than loosely patterned ODTS, which suggests length of monolayer might not the only key effect for area-selective ALD. This experiment will help us find gas phase delivery recipe of small molecules for area-selective ALD in the future. (PDF) 
April 17 Host: Steve Beaudoin, Arizona State University
Presentation guests:  
Professor Ruben Carbonell
, Department of Chemical Engineering, and Director of the William R. Kenan, Jr. Institute for Engineering, Technology and Science and the Kenan Center for the Utilization of C02 in Manufacturing, North Carolina State University
Professor Joseph DeSimone, Department of Chemistry, and the NSF Science and Technology Center for Environmentally Responsible Solvents and Processes,  University of North Carolina at Chapel Hill 
Topic:  “Dry” Processes for Microelectronics
This lecture describes the rationale for the use of CO2 as a solvent in microelectronic processes to replace aqueous and organic solvents that play such an important role in photolithography, cleaning, etching, chemical mechanical planarization (CMP) and many other steps in integrated circuit manufacturing.  With the advent of exposure tools that work at 193 and 157 nm, and device features reaching the 100 nm node, water and organic solvents can cause image collapse in vias, are incompatible with many low-k dielectric materials and because of their high surface tension and viscosity are unable to penetrate into narrow features for cleaning and particle removal.  Wet processes are also incompatible with cluster tools required for vacuum film deposition and etching processes and as a result, they mandate construction of additional clean room space.  In addition, wet processes leave vestige solvents after spin coating that can be problematic for exposure tools due to the decrease in transparency of the film.  A typical FAB processing 5,000 wafers per day will generate over 50 million liters of organic and aqueous solvent waste per year.  These are generated primarily in cleaning and etching, lithography, dry organic metal film deposition and in CMP.  The convergence of these technical and environmental problems makes it even more important to consider alternatives to current “wet” processing steps in the FAB.  
Because of its very low viscosity, high density and high vapor pressure, CO2 is an ideal solvent for many applications.  In addition, our ability to design especial polymers, surfactants, detergents, chelating agents and other chemicals that are soluble in CO2 greatly enhances the possibilities of using carbon dioxide as a solvent.  We have a comprehensive research program targeted at replacing the “wet” processes based on the use of water and organic solvents with “dry’ processes based on the use of liquid and supercritical CO2.  We consider CO2-based processes “dry” since at standard temperature and pressure CO2 is a gas.  This makes CO2-based processes amenable to use in chambers that can be evacuated and interfaced with vacuum cluster tools, standard features in FABs today.  
In this talk we will describe work aimed at designing a completely “dry” photolithography where CO2-soluble photoresists and photoacid generators are coated on the wafer surface using a novel liquid CO2 spin coater.  Development and stripping of the photoresist are carried out in CO2 in the supercritical phase.  We also highlight the major features of a free meniscus liquid CO2 coating process that is able to produce highly uniform 10 – 300 Å that might find applications in producing highly conformal coatings of lubricants and of protective materials.  Finally, we discuss work at a very early stage on the development of a novel liquid CO2 based chemical mechanical planarization process. (PDF)
April 24 Host: Stacey Bent, Stanford University
Presentation by:  Dr. Thomas Seidel, CTO, Genus, Inc.
Topic:  "ALD Reactor Architecture - ESH Implications"
The Atomic Layer Deposition processes are starting to be heavily used and researched for sub 100nm semiconductor applications. Example applications include advanced capacitors, gates and interconnect barriers. The major requirements are film conformality, electrical quality and throughput. ALD may be thermal or plasma assisted in its approach. In this lecture, various ALD reactor architectures are surveyed. 
“Flow” (vs. low pressure) ALD reactors are now dominant because of the inherent advantage of rapid purge part of the cycle and higher throughput. However, research reactors using low pressure remain useful for surface science. An additional classification of reactors includes: single wafer and batch type systems and these may also have horizontal or vertical flow designs. Furthermore, some designs have plasma-assisted capabilities that may be remote or imbedded. The qualitative relative advantages and disadvantages of the various designs are discussed. 
The guidelines for the design of ALD reactors are well known and predicated on the concept that self-saturating ALD processes are flux (temperature and chemical species) independent, which leads to transparency in substrate size and simplification in reactor design and operation. The amount of deposition (A/cycle) is largely independent of the amount of precursor above saturation, and gas dynamics and kinetics play minor roles.  These results are  -for the most part - already realized and examples or case studies will be cited.

Since the ALD reactants are separately and sequentially pulsed into the reactor, there is an opportunity to collect the nearly pure unused reactants as well. Some ALD precursors may be very expensive and make it useful to collect the unused reactant(s). A generic separation and entrapment process for collecting unused precursors in the exhaust is briefly discussed. (PDF)
May 1 Host:  David Graves, University of California-Berkeley
Presentation guest:  Walter Worth, Program Manager, Environment, Safety and Health Technology Development Group, International SEMATECH
Topic: "An Update of ESH Regulations Affecting Semiconductor Chemicals"
Abstract:  To meet the future generation technology goals in the International Technology Roadmap for Semiconductors (ITRS) a plethora of new chemicals is being screened for advanced gate stack, low k dielectrics and 157nm lithography.  This creates the need for early assessment of these chemicals for any potential ESH impacts during the R & D phase of the process development.  As part of this assessment close attention is being paid to existing and emerging ESH regulations both here in the U.S. and in Europe. 
This presentation reviews global regulatory trends, the current EPA chemicals strategy and chemical initiatives of the European Union.  It also describes in some detail the status of regulations that affect specific chemicals used by the semiconductor industry, such as such as PFOS, Pb and HMDS.  The presentation concludes with a brief review of current SEMATECH activities in the chemical data collection and ESH impact assessment of the new chemistries being evaluated for future chip manufacturing. (PDF)
May 8 Host:  Rafael Reif, Massachusetts Institute of Technology
Presentation by:  Sebastien Raoux, Acting Director of Technology, Environmental Solutions Product Division, Applied Materials Inc.
Topic: "Environmental technologies and management systems: the perspective of an equipment maker"
Abstract:  The semiconductor industry is undertaking major research and development efforts to improve the environmental friendliness of its manufacturing processes. At each technology node, semiconductor fabrication processes are amenable to change, and implementation of sustainable manufacturing practices should be favored. However, the stringent requirements of the semiconductor fabrication process can render the introduction of environmentally-friendly manufacturing techniques a challenge. In this presentation, we outline the life cycle of a semiconductor product, and highlight some of the environmental challenges the industry is facing. We examine how the Environmental Value Systems analysis (the EnV-S developed in collaboration with UC-Berkeley) can help make win-win decisions at the equipment design level. Through a few case studies, we illustrate how environmental metrics can be used to better understand manufacturing processes and implement solutions. We also describe innovative technologies that have been recently developed by Applied Materials to reduce the environmental impact of semiconductor manufacturing. Finally, we stress that one must conciliate product competitiveness and environmental friendliness, and briefly examine the role of supply chain management towards this endeavor. (PDF)
May 15 Host:  Anthony Muscat, University of Arizona
Presentation guest:  Bo Xie, University of Arizona
Topic:  "Backend Processing Using Supercritical CO2"
Abstract: Densified fluids heated and compressed to near or above their critical temperature and pressure have solvating properties that are comparable to liquids but mass transfer characteristics comparable to gases making them promising candidates for wafer cleaning applications on both the front and back end of line. Supercritical CO2 (scCO2) is currently under development in the semiconductor industry to deposit and etch metal films and remove photoresist and etching residues. We are working to define the surface reaction chemistry for Cu removal and ultra low k film cleaning and repair. The Cu removal results demonstrate that two mechanisms are operative. Pure scCO2 mechanically removed Cu(II)O selectively to Cu(0) metal. Adding the metal chelator hfacH in ppm concentrations to scCO2 chemically removed both Cu(II)O and Cu(0) metal. Work on cleaning and repairing etched and ashed blanket porous ultra low k (ULK) methyl silsesquioxane (MSQ) films shows that 5-7% by volume of the C1-C4 alcohols and carboxylic acids added to scCO2 removed H-bonded silanol (Si-OH) groups. The results indicate that n?propanol and n-butanol offered the best performance at the lowest vapor pressure of the cosolvents studied. Film repair using Si-bearing chemistries showed that hexamethyldisilazane (HMDS) and trimethylchlorosilane (TMCS) reacted preferentially with lone silanol groups in the film below processing pressures of 290 atm and reacted with both lone and H-bonded silanol groups above 290 atm. (PDF)
May 22 Host:  Duane Boning, Massachusetts Institute of Technology
Presentation by:  Professor Fiona Doyle, Department of Materials Science and Engineering, University of California-Berkeley
"Insight into Mechanisms for Passivation of Copper in CMP Slurries Containing Peroxide and Glycine"
Abstract:  Copper has been observed to passivate in CMP slurries containing glycine, when hydrogen peroxide is used as an oxidant, even under acidic conditions where no solid oxidized phases appear on the potential-pH diagram.  This passivation behavior is highly desirable for effective CMP.  In contrast, passivation is not seen in slurries of similar pH and complexing agent concentration, where the potential is increased electrochemically.  In order to model the effects of chemistry on CMP rates, we are endeavoring to better understand the mechanisms responsible for passivation in slurries containing hydrogen peroxide.  Here we report tests that characterize the degree of passivation seen in slurries containing glycine with a reasonably wide range of pH.  Kinetic experiments are consistent with the formation of a passivating film, rather than with the adsorption of inhibiting species (Fiona M. Doyle, Ling Wang and Serdar Aksu, University of California-Berkeley). (PDF)  
May 29 Host:   Srini Raghavan, University of Arizona
Presentation guests: Don Frey, Director of Marketing, CMP Products, and 
Dr. Bob Small, CMP Technical Director / CMP Applications Lab Manager, DuPont EKC Technology, Inc.
Topic: "Post CMP Cleaning for Copper, STI and Tungsten CMP Applications"
Effective Post CMP cleaning requires the removal of particulates and surface contaminants to very low levels.  At the same time it is important that no degradation occurs to the structures being cleaned and that safety, health and environmental concerns are addressed.  EKC has investigated post CMP cleaning with buffered chelating solutions (BCS) and found them to be highly effective and environmentally acceptable. Their application to various needs, including copper interconnects, will be discussed. (PDF)
June 5 Host:  David Dornfeld, University of California-Berkeley
Presentation by:  Uday Ayyagari, Graduate Student Researcher, Department of Mechanical Engineering, University of California-Berkeley
Topic:  "Environmental Cost of Ownership for Low-k Dielectric Deposition: A Case Study using the Environmental Value Systems Analysis"
Abstract: The Environmental Value Systems Analysis (EnV-S) is a software tool developed at UC Berkeley to support environmental decision-making and Design for Environment (DfE) in semiconductor manufacturing. This talk will cover the methodology for development of a new EnV-S module for low-k dielectric deposition. Selected results on evaluating Environmental Cost of Ownership (CoO) for low-k dielectric deposition technologies - SOD and CVD - will be presented. Preliminary results from a hybrid Life-cycle Assessment combining the EnV-S tool with Economic Input-Output Life Cycle Assessment (EIOLCA) will also be discussed. 
June 12 Host:  Karen Gleason, Massachusetts Institute of Technology
Presentation by:  April Ross, Massachusetts Institute of Technology
Topic:  "Chemical Vapor Deposition of Organosilicon Composite Films for Porous Low-k Dielectrics"
Abstract:  The demand for high-speed devices in today’s electronics is surging and several changes are being investigated for improvement of current devices.  At the forefront of these options is reducing the capacitance, C, of the inter-level dielectric material.  Two different pathways are being explored to lower the k-value relative to the silicon dioxide (k~4) commonly used today.  Both incorporating atoms and bonds that have a lower polarizability, such as alkyl groups, and lowering the density of the material, sterically or with the integration of air, can be employed to lower the dielectric constant.  
Creating porous films with a siloxane matrix is an avenue for introducing void space and thereby decreasing density and lowering the dielectric constant.  Incorporating polystyrene beads into an OSG film as a sacrificial porogen offers many advantages.  First, the deposition of the OSG is decoupled from that of the porogen allowing for any choice of OSG precursor and deposition conditions.  Second, the pore size and pore size distribution are controlled.  Earlier work examines OSG deposition over several stacked layers of beads dried onto a wafer.  Difficulties incurred as the films often collapsed after the beads were removed via annealing.  This is caused by both the high degree of porosity inherent in stacking the beads as well as lack of OSG film hardness.  Flowing the beads in simultaneously with the OSG precursor as it is depositing would allow for a fewer beads to be incorporated throughout the film.(PDF)
June 19 Host:  Anthony Muscat, University of Arizona
Presentation guest:  Dr. Gunilla Jacobson, Supercritical Systems, Inc.
Topic:   "Cleaning of Photoresist and Etch Residue from Low-k Dielectrics using Supercritical CO2 "
Abstract: The traditional ash and wet cleaning technologies are facing challenges as the industry moves towards porous low-k material with higher aspect ratios and dual damascene Cu technology. The traditionally oxygen based ash technology will damage porous (and even dense) carbon containing dielectric materials and the high surface tension of liquid based wet clean solvents will not be able to reach into the high aspect ratio vias as the critical dimensions are reduced to less than 0.10 µm. Wet clean solutions potentially cannot be removed from the porous material, or leave residue behind.  The use of SCCO2  as a cleaning solvent for removing photoresist and etch residue from semiconductor wafers is a novel approach to cleaning porous low-k dielectrics. The process can combine both the ash and wet clean into one step and also eliminates the need for an additional drying step. By adding only small amounts (less than 30 ml per wafer) of co-solvent the process also reduces the materials cost for cleaning, while providing an environmentally clean process.  The SCCO2 process is developed on small (1 x 1.5 cm) wafer pieces mounted in a high pressure chamber. The chamber is heated and filled with liquid carbon dioxide and then pressurized to the desired pressure. A co-solvent mixture is injected and the cleaning takes place. It is also possible to perform several cleaning/rinsing steps after each other, with each step typically taking less than two minutes. The wafer pieces are examined by optical microscope and SEM.  It will be shown that the SCCO2 process can be successfully applied to a variety of process technologies ranging from front end applications, such as removing photoresist and residue from ion implant wafers, to dual damascene structures with Cu and porous low-k dielectrics. We will also show how the process can be used to repair low-k dielectrics damaged by an ash process. This is done by restoring not only the hydrophilic surface but also the bulk material and removing trapped moisture by extraction into the supercritical fluid. 
It is clear that the SCCO2  process can replace both the traditional ash and wet clean technologies. Besides being compatible with the newest materials and technologies it will also dramatically reduce the amounts of solvents and water used. The process is a modular approach: it can be used as a stand alone application with up to eight modules on a central handler, or it can be combined with an etch tool, scrubber or metal deposition tool. This will allow both the footprint and cost of equipment in the fabs to be significantly reduced. (PDF)
June 26 Host:  Pierre Khuri-Yakub, Stanford University
Presentation by:  Utkan Demirci, Stanford University
Topic: "Environmentally Benign Deposition of Photoresist and Low-k Dielectrics"
Abstract:  Most of the semiconductor and MEMS fabrication processes require deposition of organic polymers on wafers. The current state-of-the-art method is the spin coating. This method achieves sub-micron uniformity and can cope with the throughput requirements dictated by the industry. On the other hand, over 95% of the expensive coating material is wasted. To reduce waste, we proposed the use of novel two-dimensional micromachined droplet ejector arrays to deposit photoresist and other spin-on materials used in IC manufacturing.  
Each element of the two-dimensional ejector array consists of a flexurally vibrating circular membrane placed on one face of a cylindrical fluid reservoir. The membranes have an orifice etched at their centers. The droplets are ejected through these orifices. The actuation is performed by a piezoelectric transducer placed parallel to the array on opposite side of the membrane.
We fabricated 5x5 2D single crystal silicon membrane ejector arrays with 100
mm, 300mm, 500 mm, and 1 mm membrane diameters. The single crystal silicon membranes are 1 mm thick with six standard deviation variation of 0.024 mm over an array. Water droplet ejection from various membranes of the same array at 1.2 MHz is demonstrated indicating that the devices are uniformly fabricated.
For low power and uniform operation of the devices the design parameters should be optimized. In order to achieve this purpose we constructed a finite element method (FEM) model of the device. The model consists of an array of membranes and reservoirs. The membranes are actuated by an external transducer. Absorbing boundaries are employed to avoid the reflection from the edges of the fluid boundary. First, we investigated the effect of the reservoirs on the membrane resonances. Our results showed that the quality factor of the resonance frequency is determined by the fluid reservoir height. Secondly, the cavity resonances of the silicon wafer and standing wave resonances of the transducer were calculated. Thirdly, for optimum device operation, we matched these resonances with the membrane resonances by adjusting the height of the fluid reservoir and the distance between the transducer and the array. Moreover, our simulations showed that this distance should be larger than the focal distance of the transducer in order to achieve uniform membrane displacement over the whole array. Finally, we took the displacement data on the membrane and simulated the droplet formation at the orifice by using a fluidics FEM method for calculated displacements. By employing the results of the simulations we optimized the ejector array design.  (Utkan Demirci, Goksen G. Yaralioglu, and Butrus T. Khuri-Yakub, Ginzton Laboratory, Stanford University, Stanford, California 94305)
July 3 No TeleSeminar - 4TH OF JULY HOLIDAY
July 10 Host:  David Mathine, University of Arizona
Presentation by:   David Mathine, University of Arizona
Topic: "The CMOS Biochip for Toxicity Testing"
Traditional means of determining chemical toxicity typically involve expensive and laborious animal studies.  These methods cannot keep pace with the demand for evaluating the toxicity of new chemicals introduced by industry. The advent of biochip technology promises to yield a high-throughput means of screening even complex mixtures of chemicals for toxicity. By monitoring the genetic activity of exposed cells, investigators can identify signature genetic responses that indicate toxic insult. Specifically, relative levels of gene expression between treated and control in vitro models are used to assay whether the treated model exhibits a genetic response characteristic of physiological stress.
The presentation will report on the design and production of a CMOS chip capable of performing the requisite electrochemical and optical measurements, the design and production of a driver device to orchestrate the chip’s functions, and the development of adequate in vitro models for toxicity testing. (PDF)
July 17 Host:  Ara Philipossian, University of Arizona
Presentation by:  Leslie Charns, University of Arizona
Topic:  "Thermal and Mechanical Properties of CMP Pads Containing Embedded Water Soluble Particles"
 Abstract:  The characterization, fundamental understanding, and control of the magnitude of shear forces in the pad-slurry-wafer region are an integral element in developing optimal planarization processes. In this study novel, non-porous pads containing varying amounts of embedded water-soluble particles (WSP) have been characterized and compared to a conventional porous pad (IC-1000) for ILD CMP applications. WSP pads are compared to conventional pads in terms of surface structure and topography, process temperature, and thermo-mechanical properties.  In-situ infrared thermal imaging performed at the surface of the pad (near the leading edge of the wafer) show temperatures to increase as a function of pressure and velocity. Results also indicate that the temperature at the surface of the pad can increase up to 10°C. Thermal information is shown to be a critical component in explaining the mechanism of material removal hence prompting the investigation of the effect of pad modulus properties with temperature. Mechanical properties of the pads, as measured by a Dynamic Mechanical Analyzer, show that the glass transition temperature for the WSP containing pads occur at standard CMP operating temperatures (20-40°C). Comparative storage modulus trends demonstrate steeper decreasing slopes for WSP pads than IC-1000 as pads become more flexible with temperature. The IC-1000 pad exhibits a gradually decreasing slope in the storage modulus curve, which is a sign of a highly cross-linked material. Pads containing WSP also exhibit a greater energy loss to heat as quantified by the difference between storage and elastic moduli.  Results show that there is a strong dependence of pad bulk properties when comparing grooved pads to flat pads, however there is no difference between new and used pads between 20-40°C.  (PDF)
July 24 Host:  Greg McRae, Massachusetts Institute of Technology
Presentation by: 
Greg McRae and Yue Chen,  Massachusetts Institute of Technology
Topic:  An Integrated Economic and ESH Framework for Making Technology Choices"
: This presentation will introduce a new framework that integrates both economics and EHS issues into decision making about technology choices. The need for a new approach becomes apparent even in simple cases. For example, in choosing whether to use NF3 or F2 as a CVD chamber cleaning gas many issues must be considered including: costs, toxicology, safety, etching efficiency, local and global environmental impacts. Picking which one is “best” is not straightforward. The problem is even more complicated for emerging technologies because there are many data gaps and often large uncertainties in EHS effects. The challenge is how to allocate resources to reduce uncertainties in the decision outcomes. While there has been widespread acceptance of the Sematech Cost of Ownership (COO) model the same cannot be said for EHS models. Some of the reasons for this situation will be addressed in the presentation. A particular focus will be on a new Product Input-Output Life Cycle Assessment (PIO-LCA) methodology that addresses data availability and data quality through the combination of uncertainty analysis and hierarchical modeling.  The new ESH model has the ability to vary system boundaries and generate the distribution of potential impacts rather than simple point estimates. A case study of NF3 versus F2 will be used to illustrate the importance of looking beyond the fab in an ESH assessment.  Given the same cleaning performance, when the system boundary of the evaluation is drawn only around the tool or even extended to the downstream treatment, the two technologies are similar, with F2 cleaning having slightly higher impacts.  However, once the upstream processes for producing NF3 and F2 are included, the cleaning process using NF3 clearly has higher impacts than the one using F2(PDF)
July 31 Host:  Gary Rubloff, University of Maryland
Presentation by:  Gary Rubloff, University of Maryland
Topic:  "In-Situ Metrology: the Path to Real-Time Advanced Process Control"
While real-time and in-situ process sensors have been effectively applied to fault detection, process control through course correction has been mainly focused on in-line metrologies to drive run-to-run feedback and feedforward control.  We have developed in-situ metrologies based on mass spectrometry, acoustic sensing, and FTIR techniques which enable real-time thickness metrology and control in CVD processes at a level of about 1% accuracy.  These developments open the door to real-time sensors as the basis for both fault management and course correction, i.e., for real-time advanced process control.  We have also employed in-situ metrology to develop robust control schemes for CVD precursor delivery from solid sources, and we are exploring a new spatially programmable reactor design paradigm for which real-time, in-situ sensing, metrology, and control of across-wafer uniformity is fundamental.  These advances hold promise for more efficient manufacturing through advanced process control, and with it, improved environmental metrics from that manufacturing. (PDF)  
Aug. 7 Host:  Anthony Muscat, University of Arizona
Presentation by:  Prashant Raghu, University of Arizona
Topics:  "Molecular Contamination of High-k Gate Dielectric Surfaces"
Abstract:  Hafnium oxide (HfO2) and zirconium oxide (ZrO2) are two high-k materials having the potential to replace silicon oxide (SiO2) as the gate dielectric.  Atmospheric molecular contamination (AMC) can affect the quality of the new gate dielectric film in a manner similar to SiO2.  Characterization of contaminant adsorption behavior of these high-k films should assist in deciding their potential for successful integration in silicon MOS technology. The interaction of moisture and organics (in particular IPA) as common interfacial contaminants with 5-nm HfO2 and ZrO2 films deposited by ALCVDTM was investigated using Atmospheric Pressure Ionization Mass Spectrometry (APIMS); the kinetics and mechanism were compared to that of SiO2.  HfO2 and ZrO2 have similar moisture adsorption loading, but significantly higher than that of SiO2.  However, almost all the adsorbed moisture can be removed from SiO2 and HfO2 films after a 300 oC bake under nitrogen purge, whereas ZrO2 films retain 20–30 % of the adsorbed moisture.  Experiments with isopropanol show that the adsorption loading on the three surfaces have the following order: ZrO2 > HfO2 > SiO2.  The mechanism of interactions of these contaminants with wafer surfaces was also studied using isotope labeling with D2O.  Results indicate that IPA chemisorbs on hydroxylated oxide surfaces to form a strongly bonded alkoxy species.  Thus, moisture aggravates organic contamination.  A multilayer model for adsorption of water and IPA is developed to understand the mechanism of interactions of contaminants with the three surfaces.  (PDF) 
Aug. 14 No TeleSeminar
Aug. 21 No TeleSeminar --Annual Retreat & IAB Meeting at Stanford (August 21-22, 2003 in Palo Alto, CA)
Aug. 28 No TeleSeminar
Sept. 4 Host:  Anthony Muscat, University of Arizona
Presentation guest:  Dr. Eugene Ngai, Director of Compound Semiconductor Technology, Air Products & Chemicals Inc.
Topic:  Gas Safety Presentation -- Part 1
AbstractA wide variety of chemicals (gases, liquids and solids) are used in the fabrication of semiconductor devices.  These compressed gases have a wide range of chemical and physical properties. They can present a significant hazard to the user if the systems are not properly designed or if they are not used properly. Many gases have multiple hazards.

This presentation will be in two parts. The first will be a review of the basic physical and chemical characteristics of gases in cylinders and what will be important to the user to consider for safe handling. (Compressed Gas Basics 101)
  1. Physical State
  2. Pressure
  3. Liquid Expansion
  4. Liquid Vaporization
  5. Toxicity Definitions and Classification by the Regulations (PDF)
Sept. 11 Host:  Anthony Muscat, University of Arizona
Presentation guest:   Dr. Eugene Ngai, Air Products & Chemicals Inc.
Topic:  Gas Safety Presentation -- Part 2
AbstractThe second part will categorize the gases based on their major hazard characteristics. In each category a common Semiconductor Gas will be used to highlight some of the safety issues. It will also use incidents involving these gases to emphasize what not to do and key learnings.  
  1. Highly Toxic (example Arsine)
  2. Pyrophoric (example Silane)
  3. Oxidizer (example Nitrous Oxide, Chlorine Trifluoride)
  4. Corrosive (example Hydrogen Chloride)
  5. Flammable (example Hydrogen)
  6. Inert (example Nitrogen)
  7. Self Reacting gas (example Germane)

Only by understanding these issues can we better assess the hazards of the newer gases that are constantly being evaluated to improve device fabrication or performance. (PDF)

Sept. 18 Host:  Paul McIntyre, Stanford University
Presentation by:  Paul McIntyre, Department of Materials Science and Engineering, Stanford University
Topic:  Novel Deposition Processes for High-k/Silicon and High-k/Germanium Devices
High permittivity dielectric materials and metal gate electrodes are currently being investigated by many research groups world-wide in an effort to continue the aggressive dimensional scaling of metal oxide semiconductor (MOS) devices.  Deposition-based processing methods that can achieve an unprecedented control of interface structure and composition control are required to synthesize these materials for use in future transistors.  Specific challenges include preparation of ultrathin high-k dielectric layers and workfunction-engineered gate electrodes on silicon substrates so as to achieve MOS gate stacks with an equivalent oxide thickness (EOT) of ~ 0.5 nm.  This presentation will review recent results on deposition methods for high-k metal oxide-based gate dielectrics on Si, and the structure-property relations of the resulting gate stacks.  Emphasis will be placed on HfO2 dielectrics synthesized by 1) atomic layer deposition (ALD), or 2) UV-ozone oxidation (UVO) of deposited metal precursor layers.  Prospects for synthesis of ultrathin metal interface layers that may be used to engineer the workfunctions of metal gate electrodes will also be examined.   
The development of relatively high-quality deposited gate dielectrics to replace SiO2-based dielectrics for silicon field effect transistors presents an opportunity to consider alternative materials for the semiconductor channel in such devices. There are many fundamental advantages to using Ge in the channel in place of Si.  The relative instability of GeO2 with respect to most high-k metal oxides under oxidizing conditions may avoid growth of an undesirable low-k interface layer under the deposition conditions used to form the high-k gate dielectric, in contrast to the typical situation for high-k deposition on Si.  Furthermore, use of Ge may result in lower temperatures for dopant activation compared to Si.  The larger (and better-matched) low-field carrier mobilities in Ge relative to Si result in devices that operate beyond the universal mobility model for Si MOSFETs.  Results obtained from ALD- and UVO-synthesized metal oxide dielectric layers on Ge (100) substrates will be compared.  Physical characterization of HfO2 and ZrO2 gate dielectric layers and their interfaces with cleaned Ge substrates will be emphasized.  Recently published electrical data obtained from MOSCAP structures and high-k Ge MOSFETs will also be reviewed.  (Paul C. McIntyre, Hyoungsub Kim, David Chi, Chi On Chui,* Baylor B. Triplett, and Krishna C. Saraswat*, Department of Materials Science and Engineering, *Department of Electrical Engineering,
Stanford, CA, U.S.A. 94305-4045) (PDF) 
Sept. 25 Host:  Paul Blowers, University of Arizona
Presentation by:  Dr. Michael Overcash, Chemical Engineering Department, North Carolina State University
Topic:  Life Cycle Approaches in Semiconductors and Supply Chain Systems
Abstract:  Decision-making for environmental improvement in semiconductor manufacturing has been successful using principles of pollution prevention and green chemistry.  These focus on process and chemistry changes that lead to reductions in chemical losses and energy usage.  Life cycle analysis is aimed at these same environmental improvement goals, but expands these to understand the full cradle-to-product environmental impacts.  Research has been undertaken to build the database, methods for efficient generation of life cycle inventory information, and a framework to incorporate life cycle thinking and analysis into the R & D process.  These are discussed and examples of use are given.  Life cycle often uncovers hidden benefits of green chemistry that occur in the life cycle footprint. (PDF)
Oct. 2 Host:  Duane Boning, Massachusetts Institute of Technology
Presentation by:  Dr. Marilena T. Radoiu, Senior Development Chemist, BOC Edwards
"Atmospheric Microwave Plasmas for the Abatement of Perfluorocompounds "
Abstract:  This paper describes the development and application of a non-equilibrium plasma system sustained by 2.45 GHz frequency microwaves (MW) and operated at atmospheric pressure that can effectively remove perfluorocompounds from gas streams. The technology has been tested on gas flows containing CF4, C2F6, CHF3 and SF6 to illustrate its effectiveness. As it will be presented in the following paper, successful abatement is dependent on the total gas flow, the total power level, and the concentration of CF4. (PDF)
Oct. 9 Host:  Anthony Muscat, University of Arizona
Presentation by:  Jamshid Sorooshian, Department of Chemical & Environmental Engineering, University of Arizona
Topic:  "Characterization of STI CMP Motor Current Endpoint Detection for Consumables Minimization"
Abstract:  This study investigates the feasibility and environmental implications of motor current endpoint detection for Shallow Trench Isolation (STI) Chemical Mechanical Planarization (CMP) processes.  Results indicate that repeatable motor current endpoint detection can be achieved for STI wafers with oxide pattern density variations of up to 17.4 percent.  Furthermore, results show that a dependence exists between the STI oxide pattern density variation and motor current endpoint success during polishing.  Due to the outcomes of this study, a robust motor current endpoint detection system could yield successful termination points for STI polishing, as well as reduce the need for polishing reworks.  It is estimated that the use of a successful endpoint detection system could reduce slurry usage by as much as 15 percent per polish and allow savings of roughly $200,000 per year in slurry and pad consumables for a typical IC manufacturing facility. (PDF)
Oct. 16 Host:  David Graves, University of California-Berkeley
Presentation guest:   Eric A. Hudson, Senior Engineering Manager, Dielectric Etch Core Technology Group, Lam Research Corporation
Topic:  "Trends in Dielectric Etch for Microelectronic Processing"
Abstract:  Dielectric etch technology faces many challenges to meet the requirements for leading-edge microelectronics processing.  The move to sub 100-nm device design rules increases the aspect ratios of certain features, imposes tighter restrictions on etched features' critical dimensions, and increases the density of closely packed arrays of features.  Changes in photolithography are driving transitions to new photoresist materials and novel multilayer resist methods.  
The increasing use of copper metallization and low-k interlayer dielectric materials has introduced dual-damascene integration methods, with specialized dielectric etch applications.  A common need is the selective removal of multiple layers which have very different compositions, while maintaining close control of the etched features' profiles.  To increase productivity, there is a growing trend toward in-situ processing, which allows several films to be successively etched during a single pass through the process module.
Dielectric etch systems mainly utilize capacitively coupled etch reactors, operating with medium-density plasmas and low gas residence time.  Commercial technology development relies upon plasma diagnostics and modeling to reduce development cycle time and maximize performance.
Advanced methods of process control, relying on real-time analysis of sensor data, are increasingly used to identify excursions from optimal processing conditions and to optimize tool performance. (PDF)
Oct. 23 Host:  Christopher Ober, Cornell University
Presentation by:  Victor Q. Pham, Department of Chemical Engineering, Cornell University
Abstract:  Modern advances in integrated circuit (IC) technology have presented many complex issues ranging from practical to environmental.  The increased use of organic solvents, halogenated solvents, and water in manufacturing and processing of ICs has led to a need for environmentally responsible and energy efficient processes.  Alternatives to the previously mentioned solvents have been researched and one possibility is liquid and supercritical carbon dioxide (scCO2.)
Using CO2 can be advantageous for a number of reasons.  For example, CO2 is inexpensive, nonflammable, environmentally benign, and can be completely and easily removed from other products.  In addition, scCO2 is not hindered by surface tension that can result in pattern collapse in small features and can operate within reasonable conditions. 

In this presentation, we show a number of different (positive-tone, EUV, CVD) photoresist systems that have been designed to be compatible with scCO2 processing.  A silylation method to chemically modify an existing negative-tone resist system to produce one that is positive-tone is discussed and new results are presented.  We present for the first time sub-micron lithographic imaging of a positive-tone resist developed in scCO2.  In addition, a non-fluorous resist system was developed in scCO2 to yield sub-micron lithographic patterns. Processing methods, process optimization, and understanding of polymer-scCO­2 interactions from our work with cosolvents are discussed. (PDF)
Oct. 30 Host:  Ara Philipossian, University of Arizona
Presentation by:   Ara Philipossian, University of Arizona
Topic: "Consumables Reduction in Copper CMP"
Part 1:  Comparison of Copper Disc and Copper Wafer Polishing in Terms of Their Kinetic, Tribological and Thermal Characteristics 
Part 2:  Determining the Effect of Slurry Flow Rate on the Tribological, Thermal and Removal Rate Attributes of Copper CMP
Abstract:  Real-time coefficient of friction, removal rate, pad temperature transient and Interfacial Interaction Index were employed to identify and compare the Chemical Mechanical Polishing processes involving copper deposited wafers and copper metal discs.  Coefficient of friction and pad temperature transients were slightly higher for the copper deposited wafers. This difference was explained by taking into account the storage modulus of the pad, as well as the significant differences in the bevel shape of discs vs. wafers. Results were consistent with the differences in the Interfacial Interaction Index. Removal rate results were also slightly higher for copper wafers suggesting consistent with a thermally dependent copper removal mechanism. In spite of the minor differences among the two substrates, copper discs are considered to be viable and more economically feasible replacements for copper deposited wafers given the fact that this study indicated that the choice of the copper substrate did not affect the key conclusions reached in this study. Furthermore, the process is examined experimentally and theoretically as a function of slurry flow rate and the product of the applied wafer pressure and relative sliding speed (pV). It is observed that under constant tribological conditions, the removal rate at any fixed value of pV generally decreases as the slurry flow rate increases. This is explained as a reduction in reaction rate due to increased cooling of the wafer surface by the slurry. At a fixed flow rate, it is further observed that the removal rate does not necessarily increase monotonically with pV. The rate may instead depend on the particular pressure and velocity chosen at a fixed value of their product. The dependence occurs through the coefficient for convective heat transfer between the wafer and the slurry, and the heat partition factor, which determines the raction of the total frictional power that heats the wafer. Rates are found to be explainable with a Lagmuir-Hinschelwood model with mechanical and chemical components. 
[Z. Li 1, S. Rader 2, P. Lefevre 2, K. Ina 3, L, Borucki 4, D. Boning 5 and A. Philipossian 1 :  1 Department of Chemical & Environmental Engineering, University of Arizona, Tucson, AZ USA; 2 Fujimi Corporation, Tualatin, OR USA; 3 Fujimi Incorporated. Kagamigahara, Gifu Prefecture JAPAN; 4 Intelligent Planar, Mesa, AZ USA; 5 Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA USA] (PDF)
Nov. 6 Host:  Greg McRae, Massachusetts Institute of Technology
Presentation by:  Gregory J. McRae (and Yue Chen), Department of Chemical Engineering, Massachusetts Institute of Technology
Technology Choices in the Presence of Uncertainties – An update on the Economic and Environmental Issues Influencing the Choice of NF3 vs. F2 as a Chamber Cleaning Gas
Abstract:  A new decision-making framework has been constructed to help evaluate technology choices when there are uncertainties in the technology itself, the cost of ownership (COO) and the environmental impacts.  A key feature of the new approach is the use of Process by Product Input-Output Life Cycle Assessment (PIO-LCA) to calculate various categories of environmental impacts.  Particular attention is paid to the role of system boundaries (i.e. tool, process, fab,..) and their impacts. The environmental assessment modeling framework has also been linked to a cost of ownership model to expand the range of decision choices associated with picking which technology is “best”.  A case study comparing NF3 and F2 as the cleaning gas in the CVD chamber is used to illustrate the application of the framework.  It was found that the LCA environmental impacts of the NF3 cleaning are around 2.5 times that of the F2 cleaning.  The ratio is most sensitive to the power required for the two processes.  The study shows that with uncertainty analysis, large variability in inputs does not necessarily lead to a low confidence level in decision outcome. (PDF)
Nov. 13 Host:  Stephen Beaudoin, Purdue University
Presentation by:  Sean K. Eichenlaub, Department of Chemical and Materials Engineering, Arizona State University 
Topic:  "van der Waals and Electrostatic Interactions in Particle Adhesion"
Abstract:  Adhesion between particles and surfaces is important in many processes including chemical mechanical planarization (CMP) and post-CMP cleaning in the semiconductor industry.  Improved understanding of particle adhesion is required to develop improved processes to clean particles from wafers. This work combines basic adhesion equations with computer simulations to model van der Waals (vdW) and electrostatic double layer interactions for real particles in contact with a surface.  A previously developed vdW adhesion model was used to determine Hamaker constants for materials of interest in the semiconductor industry.  Comparison of these Hamaker constants with theoretical values allowed some limitations of the vdW adhesion model to be realized.  Specifically, the previous model assumed surface roughness could be approximated with a combination of ideal hemispheres, however this assumption overestimated the force in systems that had asperities larger than 10 or 15 nm.  A method using the Fourier transform to generate more accurate surface roughness models was developed.  It was found that the Fourier transform gave accurate predictions in all cases.  The vdW adhesion model with an accurate description of surface roughness was also used to examine electrostatic double layer interactions.  A boundary element technique was used to solve the Poisson-Boltzmann equations and account for the roughness of the surfaces and the geometry of the particle.  The combined vdW electrostatic model accounts for the effects of surface roughness, particle geometry, and deformation on the adhesion force.  The parameters required to describe these effects were characterized experimentally and used in the model simulations.  The model was validated through comparison with experimental measurements made with an atomic force microscope (AFM) using materials of interest in post-CMP cleaning.  (PDF)
Nov. 20 Host:  Rafael Reif, Massachusetts Institute of Technology
Presentation by:  Gary Loh, DuPont's Electronic Gases Group
Topic:  "PFC Emission Reduction in Installed-Base CVD Tools:  Some Recent Fab Results"
AbstractThe industry's goals for PFC emission reduction have been greatly aided by the development of NF3-based processes for chamber cleaning in newer-generation CVD tools. However, there are many existing fab tools for which retrofitting such an option presents significant challenges. So, there is an opportunity for other options which provide both process and ESH benefits with minimal conversion time and resources. This presentation will highlight two of these alternatives. First, optimization of the earlier standard C2F6-based cleaning processes will be briefly considered.  Second, "drop-in" replacement by other CxFy-based processes will be discussed in more detail. The emphasis will be on end user studies showing both the performance of the cleaning step, as well as results on the critical film and hardware performance parameters for the CVD process itself. (PDF)
Dec. 4 Host:  Srini Raghavan, University of Arizona
Presentation guest:  Dr. Cawas Cooper, Senior Research Associate; Dr. Juan Burdeniuc, Senior Principal Research Chemist
Air Products and Chemicals, Inc.
Topic:  "Advanced Wet Oxidation Process for Treatment of Waste Streams Containing Organic and Inorganic Nitrogen Compounds"
Air Products has developed Wet Oxidation (WO) technology for treating the effluents from the dinitrotoluene (DNT) and toluenediamine (TDA) process.  The salient features of this process, which is covered by many patents,  will be discussed in this working seminar to make others aware of the WO process, its capabilities, and benefits with intent to explore potential applications of WO in the Electronics industry.  The presenters would like to hear about the types of waste streams and treatment challenges facing the Electronics industry and evaluate feasibility of using WO. (Presentation not available)
Dec. 11 Host:   Stacey Bent, Stanford University
Presentation by:  Rong Chen, Stanford University
Topic:  "Selective Surface Preparation and Templated Atomic Layer Flim Deposition"
Abstract:  Gate dielectrics with permittivities greater than that of SiO2 are required to continue the downward dimensional scaling of MOSFETs. Among many possible deposition techniques, atomic layer deposition (ALD) is very promising for preparing high-k dielectric materials because it can produce high quality films with excellent conformality and precise film thickness control. While ALD inherently provides nano-scale control of materials in the vertical direction, we are investigating an area-selective ALD technique that will enable nano-scale definition of the lateral structure. Our research emphasizes controlling the substrate surface chemistry in order to impart spatial selectivity to ALD. Availability of area-selective ALD processes for the application of gate dielectric and gate electrode deposition could substantially reduce the number of lithography, etch, and cleaning operations required for integrated circuit fabrication. 
We have focused mainly on HfO2
and ZrO2 as the high-к gate dielectric layers in the ALD process because of their compatibility with conventional MOS device processing. We will show that well-controlled self-assembled monolayers (SAMs) are efficient deactivating agents to block the ALD chemistry in the growth of HfO2 and ZrO2, and that the efficiency of blocking depends strongly on the quality of the SAMs and the chain length of the attached layer.
Three important factors for the quality of SAMs formation
are studied by a variety of analytical techniques. We find that it is crucial to choose deactivating agents with high reactivity, low steric effects and minimum chain length in order to form condensed, highly hydrophobic film for the deactivation. The analysis provides insight into the mechanism of deactivation and ALD growth. Formation of SAMs by gas dosing has been investigated as an alternatively delivery method, allowing for the in-situ selective attachment of deactivating agents and enabling a dry process for area-selective ALD. (PDF)
Dec. 18 Host:  ERC Students -- Jam Sorooshian 
Presentation guest:  Dr. Dale Hetherington, Sandia National Laboratories
Topic:  "CMP Processing Issues for MEMS Fabrication Technology"
Abstract:  This talk will review the development needs and concerns for CMP processing in a MEMS fabrication environment.  Although the material systems are similar to those used in microelectronic circuit fabrication, the topography and film deposition thicknesses vary significantly; for example, the initial topography during typical MEMS fabrication can exceed 2 microns in step height.  This talk will focus on the specific polishing needs that are required for the successful fabrication of MEMS devices and it will also discuss the benefits of using CMP to enable a new class of MEMS structures and applications. (PDF)
Dec. 25 No TeleSeminar - CHRISTMAS HOLIDAY

Report Changes : Top : Back