SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing (ERC)

                                                          **  Bringing Sustainability to Semiconductor Manufacturing **

A multi-university research center leading the way to environmentally friendly semiconductor manufacturing, sponsored by the Semiconductor Research Corporation's Global Research Collaboration (GRC) Research Program



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- 2002 -
Jan. 3, 2002 No TeleSeminar--HAPPY NEW YEAR!
Jan. 10 Host:  Charles Musgrave, Stanford University
Presentation by:  Charles Musgrave, Stanford
Topic:  "Simulations of Chemical Reactions for Semiconductor Processing" (PDF)
Jan. 17 Host:  Anthony Muscat, University of Arizona
Presentation by:  Mr. Peter Dahlgren, Program Manager-ESH Division, International SEMATECH
Topic:  "Standardization of ESH Metrics for Semiconductor Manufacturing Equipment" (PDF)
Jan. 24 Host:  Christopher Chidsey, Stanford University
Presentation by:  Chris Chidsey, Stanford University
Topic:  "Toward a Molecular-Scale Nanoelectronics" (PDF)
Jan. 31 Host:  David Dornfeld, University of California-Berkeley
Presentation by:  David Dornfeld, UC-Berkeley
Topic:  "An Integrated Model of Chemical Mechanical Planarization" (PDF)
Feb. 7 No TeleSeminar
Feb. 14 No TeleSeminar - ERC Annual Review Meeting
Feb. 28 Host:  David Mathine, Optical Sciences, University of Arizona
Presentation by:  David Mathine, U of A
Topic: "Biochip and Microarrays for Rapid Assessment of Chemical Toxicity" (PDF)
March 7 Host:  Srini Raghavan, University of Arizona
Presentation guest:  Philippe Chelle, Product Manager, Advanced Planarization, EKC Technologies, Inc.
Topic:  "CMP Market in the Eyes of a Chemical Supplier" (PDF)
March 14 Host:  Paul Blowers, University of Arizona
Presentation by:  Paul Blowers, U of A
Topic:  "Integration of Semiconductor Manufacturing Concerns in a Green Design Course" (PDF)
March 21 Host:  David Graves, University of California-Berkeley
Presentation guest:  Matthew Richter, Director-West Coast Operations, MKS Instruments, On-Line Products Group
Topic:  "IR Spectroscopy for Process Diagnostics and Control" (PDF)
March 28 Host:  Krishna Saraswat, Stanford University
Presentation by:  Ben Shieh, Stanford University
"Use of Air-Gaps to Reduce IC Interconnect Capacitance" (PDF)
April 4 Host:  Ara Philipossian, University of Arizona
Presentation by:  Leslie Charns, University of Arizona
Topic:  "Effect of Pad Conditioning Methods on Wafer-Slurry-Pad Coefficient of Friction" (PDF)
April 18 Host:  Stacey Bent, Stanford University
Presentation by:  Collin Mui, Stanford University
Topic:  "Surface Modification for Selective Atomic Layer Deposition of High-k Dielectric Materials" (PDF)
April 25 Host:  Rafael Reif, Massachusetts Institute of Technology
Presentation guest:  Laura Mendicino, Principle Staff Engineer and Manager of the Environmental Process Initiatives Department in Advanced Process Development and External Research, a division of Digital DNA Laboratories, Motorola
Topic:  "Addressing EHS Issues with Advanced Gate Stack Processes" (PDF)
May 2 Host:  Anthony Muscat, University of Arizona
Presentation guest:   Dan Hakes, Senior Product Steward Specialist, Specialty Materials Market Group, 3M Company
Topic:  "Safety and Health Evaluations of Perfluoroalkanesulfonyl (PFAS) Based Surfactants for Semiconductor and Microelectronics Manufacturing" (PDF)
May 9 Host:  Stephen Beaudoin, Arizona State University
Presentation Guest:  Steve Beaudoin, ASU
Topic: "Update: Brush Scrubbing for Post-CMP Cleaning" (PDF)
May 16 Host:  Christopher Ober, Cornell University
Presentation by:  Chris Ober, Gina Weibel and Victor Pham, Cornell University
Topic:  "Overview and Update: Supercritical CO2 in Microelectronics Processing" (PDF)
May 23 Host:  Pierre Khuri-Yakub, Stanford University
Presentation by:  Utkan Demirci, Stanford University
"Environmentally Benign Deposition of Photoresist and Low-k Dielectrics" (PDF)
May 30 Host:   Paul McIntyre, Stanford University
Presentation by:  Shriram Ramanathan, Stanford University
"Physical and Electrical Characterization of Ultra-Thin Gate Stacks and Interfaces" (PDF)
June 6 Host:  Karen Gleason, Massachusetts Institute of Technology
Presentation by:  Yue Chen, MIT
Topic:  "Treatment of Uncertainties in ESH Assessments: New Approaches and Data Needs" (PDF)
June 13 Host:  Anthony Muscat, University of Arizona
Presentation by:  Professor Rick Reidy, Materials Science Department, University of North Texas
Topic:  "Supercritical Drying and Repair of Ultra Low-k Films" (PDF)
June 20 Host:  Duane Boning, Massachusetts Institute of Technology
Presentation by:  Dr. Tamba Tugbawa, MIT
Topic:  "Chip-Scale Modeling of Pattern Dependencies in Copper CMP Processes" (PDF)
June 27 Host:  Srini Raghavan, University of Arizona
Presentation by:  Subramanian Tamilmani, University of Arizona
Topic:  "Electrochemical Treatment of Waste Water Using Boron Doped Diamond (BDD) Electrodes" (PDF)
July 4 No TeleSeminar-4TH OF JULY HOLIDAY
July 11

Host:  David Graves, University of California-Berkeley
Presentation guest:  Dr. Xing Chen, Senior Scientist, MKS ASTex Products
Topic:  "ASTRON -- A Toroidal Plasma Source and Its Applications" (PDF)

July 18 Host:  Jim McVittie, Stanford University (Krishna Saraswat)
Presentation by:  Marci Liao, Stanford University
Topic:  "Experiments and Modeling of Mass Transfer for Cross-Contamination in Plasma Processes" (PDF)
July 25 Host:  Anthony Muscat, University of Arizona
Presentation by: 
Niraj Rana, University of Arizona
"Role of Organic and Moisture Contamination in Gate Dielectric Degradation" (Niraj Rana, Prashant Raghu, and Farhang Shadman--University of Arizona) (PDF)
Abstract:  The presentation will discuss the fundamentals of gate oxide degradation due to interfacial organic contamination.  Results will also be presented on trace-level moisture and IPA contamination of ALD deposited hafnium oxide and zirconium oxide films as compared to that of silicon oxide.
Aug. 1 Host:  Gary Rubloff, University of Maryland
Presentation guest:  Dr. John A. T. Norman, Schumacher
Topic:  "Copper CVD: Applications and Potential Recycle" (PDF)
Abstract Copper CVD: Applications and Potential Recycle
Copper CVD for semiconductor applications is described using the commercial copper precursor CupraSelect. The unique chemistry  of copper film growth using this fluorinated precursor centers on a disproportionation reaction where for every atom of copper deposited in the CVD chamber, a divalent volatile copper complex byproduct is formed which contains the fluorinated ligands of the CupraSelect molecule. Since this divalent byproduct is thermally stable it passed unchanged through the vacuum pump of the CVD chamber after which it can be collected as a solid in a simple cold trap. In this way no volatile species containing either fluorine or copper are released into the environment. Additionally, the divalent copper by-product can then be reprocessed into fresh CupraSelect. 
Aug. 8 Host:  Greg McRae, Massachusetts Institute of Technology
Presentation by: 
Greg McRae, MIT; Yue Chen, MIT
Topic:  "Data Implementations for ESH in the Semiconductor Industry" (PDF)
Abstract:  Compared to those used in economic evaluation, the data used in the environmental evaluation are more uncertain and less widely available.  Rather than the computation of the evaluation models, the collection and maintenance of data have been the main barrier for the wide application of environmental evaluation.  This talk will discuss the database structure, the differentiation of data of different qualities, and the estimation of the boundaries for evaluation factors using known properties.  Using Bayesian probability distribution functions as a means to combine data of different qualities without diluting the information content of the high quality data will be promoted.
Aug. 15 No TeleSeminar
Aug. 22 No TeleSeminar -- Retreat Meeting at Stanford
Aug. 29 No TeleSeminar 
Sept. 5 Host:  Ara Philipossian, University of Arizona
Presentation by:  Leslie Charns, University of Arizona
Topic:  "Characterization of CMP Pads Containing Embedded Water Soluble Particles" (PDF)
Abstract: Novel pads incorporating different amounts of embedded water soluble particles (WSP) have been characterized and compared to conventional porous pads. The work discusses the role of WSPs in imparting desired degrees of porosity on the surface of the pad during polishing. WSP pads are compared to conventional pads in terms of ILD removal rate measurements, wafer-slurry-pad coefficient of friction analysis, scanning electron microscopy, surface profilometry, and real-time pad thermography. Removal rate results indicate polishing with WSP pads to be Prestonian in nature (similar to conventional porous pads). A decrease in removal rate at high combinations of pressure and velocity is observed during in-situ conditioning with WSP pads. This trend is reversed when conditioning is performed ex-situ. Frictional analysis indicates that polishing with WSP pads proceeds via boundary lubrication (similar to conventional porous pads). In-situ IR thermal imaging performed at the bow wave and on the surface of the pad (near the leading edge of the wafer) shows temperatures to increase linearly as a function of pressure and velocity. Results also indicate large transient effects in temperature during short polish times. Thermal information is shown to be a critical component in explaining the mechanism of material removal. (PDF)
Sept. 12 Host:  Rafael Reif, Massachusetts Institute of Technology
Presentation by:  Sue Ross, Texas Instruments
Topic:  "TI Chemical Screening Process" 
AbstractTexas Instruments (TI) has adopted a program for the selection of chemicals and gases at its fabrication facilities worldwide. The new program replaces a number of informal programs and provides a more disciplined, standardized approach. A major benefit is that environmental, safety and health concerns will be now be addressed in the beginning when TI engineers are considering making changes in manufacturing processes or using new chemicals and gases.  This program will be used whenever TI considers using a new material, makes a change in its manufacturing process or uses a process or material that's new to a specific site. In addition, it provides steps to take whenever new environmental, health or safety information is available for a material or process that is being used at a TI facility.  The program is designed to help ensure that TI's processes and materials are safe and environmentally friendly. By addressing these issues in the beginning when TI engineers are considering making changes that will require new chemicals or gases, the company can eliminate any potential problems before they become a part of the manufacturing process. Also, evaluating these issues early in the planning process can be more cost effective and can help the company move new products from design to market faster.  Finally, the new program will help the company make sure that it's compliant with government regulations throughout the world. (PDF)
Sept. 19 Host:  Paul Blowers, University of Arizona
Presentation by:  Tao Zhu, Graduate Student, Department of Chemical and Environmental Engineering, University of Arizona
Topic:  "A Life Cycle Analysis Approach for Making Greener Semiconductor Products"
The semiconductor industry is a relatively clean industry compared to most older industries, and it is important for our industry to move to the forefront of sustainable development. Fostering world economic growth based on sound environmental practices, we should be committed to addressing environmental issues in a cooperative, "pre-competitive" manner. Growth and technological progress both drive the semiconductor industry to be proactive: to anticipate, and avoid, problems rather than correcting problems after they occur.  The semiconductor industry has established an excellent Environmental, Safety and Health (ESH) performance record and we should continue to be proactive in these areas. To achieve these objectives, we should Integrate ESH CONSCIOUS DESIGN considerations and optimization into the design of products, manufacturing processes, and the selection of chemicals, facilities, and new buildings. We should also apply, where appropriate, life-cycle considerations (LCA) to reduce the environmental impact of the final products. By using LCA, we can achieve cooperative approaches to protecting the global environment.  In effect, we can stay committed to sound, scientifically based, positive environmental policies, while recognizing the major contribution the semiconductor industry is making worldwide to the economy as we continue to work toward protection of the global environment. (PDF)
Sept. 26 Host:  Stephen Beaudoin, Arizona State University
Presentation by:   Guatam Kumar, Arizona State University
Topic:  "Progress Report on Optimization of Spin Cleaning"
Abstract: Progress Report on Optimization of Spin Cleaning: A Partnership between ASU,
SEZ America, and the CEBSM. Spin cleaning is one of the methods used to remove particles from a wafer surface. In order to estimate particle removal in the spin cleaning system, the van der Waals, electrostatic repulsion and the hydrodynamic removal forces need to be determined. The van der Waals force was found to be a function of the size of the particle adhering, the system Hamaker constant, particle- surface contact area and the particle-surface separation distance. The electrostatic force was found to be a function of particle size, particle and surface zeta potentials and the pH of the medium. The cleaning model under consideration takes into account removal by two processes occurring simultaneously - the undercutting of the wafer surface and the application of hydrodynamic force to the adhering particles. Times required for particle removal via etching alone in the absence of fluid flow have been calculated.  Prediction of the hydrodynamic removal force is dependent on the velocity profile in the boundary layer at the solution/wafer interface. As a first approximation, the spin cleaning system is assumed to consist of an infinite fluid. The dimensionless velocity profiles have been computed using this approximation. The velocity profiles obtained from this prediction are to be used to estimate the hydrodynamic removal force. Combined with the undercutting, the predicted hydrodynamic removal forces are to be used to predict removal times for the spin cleaning system and to form the basis of an optimization protocol. This method is a generalized approach to wafer cleaning and can be extended to apply to systems with different chemistries and flow patterns. (PDF)
Oct. 3 Host:  Anthony Muscat, University of Arizona
Presentation guest:  Allen Bowling, Texas Instruments
Topic:  "Future Challenges for Cleaning in Advanced Microelectronics"
AbstractWafer cleaning and surface preparation have always been very important in achieving high yields in semiconductor manufacturing.  With the continued scaling of devices below 100 nm and the proliferation of new materials in advanced devices, wafer cleaning and surface preparation will have an even greater impact in the future.   This paper will focus on the challenges for wafer cleaning and surface preparation for the next several silicon CMOS technology nodes.  This will include discussions of single-wafer wet cleaning, clustered processing/cleans,  cleaning of very high-aspect ratio vias with porous low-k dielectric materials (including supercritical carbon dioxide cleaning),  post-CMP cleaning, and new materials cross-contamination control.  It will also be emphasized that the ESH impact of wafer cleaning must be considered during development to ensure that we implement ESH-friendly processes. (PDF) (MP3 Audio)
Oct. 10 Host:  Charles Musgrave, Stanford University
Presentation by:  Charles Musgrave, Stanford
Topic:  "Simulation of High-K Gate Deposition"
Abstract:  Atomistic Simulations of Atomic Layer Deposition of High-K Gate Stacks
The development of quantum mechanics in the 1920’s laid the groundwork for a first principles description of chemical processes. However, it hasn’t been until the last decade that advances in theoretical methods and computers have made the accurate simulation of chemical reactions practical. Consequently, quantum simulations have become increasingly useful tools to study the detailed atomistic mechanisms and kinetics of chemical reactions. This is especially important for the case of film growth since much of the atomistic detail of the process is not accessible experimentally.  
Possibly the most severe technical issue facing the semiconductor industry is finding a replacement for SiO2 as the gate dielectric in MOSFET integrated circuits. Two leading candidates are ZrO2, and HfO2 and their silicates grown using atomic layer deposition. However, relatively little is known about the detailed chemistry for growing these materials. We use density functional theory to elucidate the atomistic details of depositing these materials by ALD, including the chemical mechanisms and associated kinetics. We also briefly present results for ALD of Al2O3 and deposition of SiO2, and Si3N4. The results of these simulations lead to an explanation for several unanswered questions regarding the deposition of these materials, including the submonolayer effect in ALD of ZrO2, and HfO2 using chloride precursors.

Keywords: Atomistic simulations, surface chemistry, quantum chemistry, atomic layer deposition, ZrO2, SiO2,, Si3N4, nanolaminates, chemical mechanisms, density functional theory, MOSFET, film growth,
high-k dielectrics. (PDF)
Oct. 17 Host:  David Dornfeld, University of California-Berkeley
Presentation by:  Nikhil Krishnan and David Dornfeld, UC-Berkeley
Topic:  "Environmental Value Systems (EnV-S) Analysis Discussion--Background and Connections with Life Cycle Assessment (LCA)" 
Abstract:  In this discussion, we will present some background to the EnV-S analysis and a case example - in the destruction of PFC's from etch tools.
Given the economic relevance of the semiconductor industry and the rapid rate of change, it is important to examine the environmental impacts of processing, including life cycle effects.  In this presentation, we first perform a quick environmental analysis of semiconductor manufacturing using current, publicly available databases.  This includes first order 'top-down' life cycle analysis using Economic Input Output Life Cycle Assessment (EIOLCA) methods.
Gaps in such analysis (uncertainties, the ability to effect change, the lack of consistent metrics, etc) leads on to a discussion on a 'bottom-up' Design for Environment (DFE) tool, the EnV-S, that has been developed to facilitate inclusion of specific environmental factors in equipment design/selection and process decisions.  The main metric to compare environmental factors is an environmental cost of ownership metrics.  Other metrics used include process-specific environmental factors (such as water, energy use), manufacturing performance factors (uptime, reliability) and health factors (multi-criteria hazard analysis).    In this presentation, we will focus on the use of the EnV-S to enable comparative analysis of technologies to destroy PFC's from dielectric etch tools.
The presentation will conclude with ideas for future work - to bridge the gap between bottom-up and top-down analysis by linking up specific EnV-S approach with broader supply chain and life-cycle factors.  A proposed avenue of research will involve using the EnV-S (i)  in conjunction with Economic Input Output (EIO) approaches and (ii)  with SETAC style life cycle approaches to develop a hybrid analysis. (PDF)
Oct. 24 Host:  Anthony Muscat, University of Arizona 
Presentation guest:  Dawn Speranza, Low-k ESH Impact Assessment Project Manager, International SEMATECH
Topic:  "Pro-Active Approaches in the Semiconductor Industry Toward Chemical Management"
AbstractIn 1999, International SEMATECH initiated a project focused on the ESH assessment of new semiconductor manufacturing chemicals.  The objective of this project was to identify a commonly accepted set of ESH criteria needed for early assessment of new chemicals and processes.  The ESH Data Assessment project delivered three key results:
1.       Development of a “chemical matrix”.  This matrix is a list of approximately 80 ESH data sets used to perform an effective ESH assessment of a new chemical.  It also specifies the desired point in the process development timeline at which each of these data sets should be made available.  
2.       Formation of the Chemical Data Council (CDC).  This group, which includes chemical manufacturers and semiconductor manufacturers, was instrumental in defining the criteria included in the chemical matrix.  Its current charter includes several objectives aimed at improving communication between ISMT members and suppliers regarding the chemical data acquisition process.  The ultimate objective of the industry, as defined by the International Technology Roadmap for Semiconductors, is to establish a common algorithm for the identification, access, and acceptance of chemical risk through the partnership of suppliers and device makers.
3.      Establishment of three new ISMT projects that picked up where the original project left off, applying the principles and data expectations to three key ITRS-driven technology areas: advanced lithography, advanced gate stack, and low-k interconnect.  Each of these technologies is exploring innovative processes that include new chemistries and applications.  The new ESH data assessment process provides direction on how to assist the evaluation of these new technologies to ensure that proper consideration of ESH impacts takes place. (PDF)
Oct. 31 Host:  Gary Rubloff, University of Maryland
Presentation by:  Wei Lei, University of Maryland
Topic:"Energy Usage and Mass Balances in a Dynamic Cu CVD Process Cycle" (Wei Lei, Adam Melvin, Soon Cho, and Gary Rubloff) 
Abstract:  We have previously investigated components of mass balance (reactant utilization), energy consumption (wafer heating), and manufacturing cycle time using a dynamic simulation of the Cu CVD unit process as a prototype system.  The simulator is based on a physical model of the process and equipment, and captures the essential dynamic behaviors as well as the time-integrated behaviors through the process cycle. We have since expanded and enhanced these studies to obtain a more comprehensive picture of the
important factors in these metrics.  We have incorporated energy costs associated with pumping equipment and other components along with the previously treated wafer heating component of energy usage in the Cu CVD process.  In fact, pumping systems not only consume more energy than wafer heating and other factors, but their energy usage varies considerably depending on the details of the pump types chosen, both in average power through the process cycle and in dynamic power fluctuations that occur during key transitions of the process cycle.  Accordingly, there may be real ESH benefit in working closely with component supplies to choose components that are adequate to the product performance and manufacturing cost metrics, and at the same time beneficial to ESH metrics. In addressing mass balance from the perspective of reactant utilization and its relation to process cycle time as a function of pressure, temperature, and gas flow rates, both win-win and trade-off situations emerge.  The former is easy to treat, but a more careful analysis methodology is needed to manage tradeoff situations.  We have begun to outline an approach to this challenge which includes
consideration of manufacturing cost components and also linkages to ESH impacts beyond the factory. (PDF)
Nov. 7 Host: Anthony Muscat, University of Arizona
Presentation by:  Silke Hermanns, Fab 30 Environmental Department, Advanced Micro Devices Inc.
Topic:  "Using the LCA Method for Identifying Resource Conservation Priorities at AMD Saxony"
AbstractIn this discussion we will present a project recently conducted at AMD Saxony to identify priorities for resource conservation using elements of Life Cycle Analysis (LCA) methodology. Apart from identifying resource conservation priorities, another goal was to identify the LCA method’s shortcomings and existing gaps in regards to its applicability to analyze semiconductor manufacturing.  Life Cycle Analysis is a tool to quantify potential environmental impacts along the whole life cycle of a product from raw material acquisition to its disposal at the end of its useful life. To conduct a Life Cycle Analysis a Life Cycle Inventory of all material and energy flows associated with the product’s life cycle is created as a first step, followed by an environmental impact assessment and an interpretation of results. In this project LCA methodology was used to analyze only the manufacturing phase of semiconductor devices. The LCA method was chosen because it also allows consideration and quantification of environmental impacts along the supply chain of energy and chemicals prior to the actual manufacturing processes. We performed a “black box” input-output analysis of all material and energies, which surpassed the system borders of the so-defined system “AMD Saxony” in 2001. The next step was to collect life cycle inventory data of selected high volume chemicals from LCA databases. An impact assessment, using substance specific impact factors was conducted to translate life cycle inventory data into environmental impact potentials of eight categories. In a final interpretation energy, nitrogen and water treatment chemicals, such as NaOH, HCl and KOH were identified as priorities for resource conservation.  A major shortcoming was that many data for the life cycle inventories of semiconductor specific chemicals were not available and default data had to be used. (PDF)
Nov. 14 Host:  Paul McIntyre, Stanford University
Presentation guest:  Amitabh "Andy" Singh, Stanford University
Topic:  "Investigation of Copper Impurities on Silicon Surfaces using X-ray Absorption Near Edge Spectroscopy and Total Reflection X-ray Flourescence"
Abstract:  Trace metal contamination during wet cleaning processes on silicon wafer surfaces is a detrimental effect that impairs device performance and yield. Determining the concentration and chemical state of deposited impurities helps in understanding how silicon surfaces interact with chemical species in cleaning solutions. However, since impurity concentrations of interest to the semiconductor industry are so low, conventional techniques such as x-ray photoelectron spectroscopy cannot be applied. Nonetheless, chemical information on trace levels of contaminants can be determined with x-ray absorption near edge spectroscopy (XANES) in a grazing incidence geometry. In this study, silicon samples were dipped in oxygenated as well as de-oxygenated ultra pure water (UPW) with copper concentrations of ranging from 10 ppt to 500 ppb. These samples were first analyzed using synchrotron radiation total reflection x-ray fluorescence (SR-TXRF) to determine the surface concentration of copper deposited on the silicon surface.  Then the samples were analyzed using XANES in fluorescence yield mode to determine the oxidation state of deposited copper trace contaminants. It was found that copper impurities on the silicon surface from deoxygenated UPW solutions were predominantly metal in character, while copper impurities deposited from the oxygenated solution showed more oxide character.  Lastly, the Cu Ka fluorescence signal was measured as a function of the angle of incidence of the incoming x-rays for the 20 ppb samples to determine whether the copper deposits were atomically dispersed or particle like in nature and if so, the size of the particles. (PDF) 
Nov. 21 Host:   Jim McVittie, Stanford University
Presentation by:  Dr. Pawan Kapur, Stanford University
Topic:  "Problems with Scaling Copper Interconnects and Near-term Alleviation with ALD Barrier Technology"
Silicon integrated circuits miniaturization paradigm, while conducive for devices leads to steady interconnect deterioration to a point where they can become performance bottleneck. In this talk, we will discuss the problems with interconnect scaling and the impact of technology effects such as Cu diffusion barrier, electron surface scattering and realistic operational temperatures on interconnect performance metrics. These effects were previously ignored in assessing interconnect scaling problems.
We first establish realistic resistivity trends for Cu in the future with various barrier deposition technologies, thicknesses and surface quality assumptions. We show the extent of improvement in future Cu resistivity with ALD technology compared to other barrier deposition techniques such as Ionized PVD. Subsequently, both delay and power for interconnects is quantified in this light. Delay is calculated using repeaters. Repeaters efficiently reduce delay of long wires. Power calculations for interconnects also include the penalties due to repeaters. Whereas, a thin ALD technology controls the deterioration of interconnects in the near term future, ultimately, architectural changes or alternate interconnect technologies may be needed. Optical interconnects are very briefly discussed as a long-term replacement possibility for specific interconnect applications. (PDF)
Dec. 5 Host:  Farhang Shadman, University of Arizona
Presentation guests:  
Karl Olander, Executive Vice President
Jose Arno, R&D Director, Materials/Systems Integration Group
Advanced Technology and Materials, Inc. (ATMI)
Topic:  "Developments in the Management of Exhaust in a Fab"
AbstractSEMATECH estimates the cost of ventilation in a fab at $10 per scfm/year in addition to combined capital and installation costs estimated at $75-100 per scfm/year.  This paper describes an Air Manager System (AMS) designed to control vapor emissions emanating from open baths containing hazardous liquids.  The AMS provides a collimated flow of air across the tank creating a virtual wall that confines vapor emissions.  Results from tests performed in our laboratories and in a manufacturing facility indicate efficient containment while significantly reducing ventilation requirements.  The seminar also includes considerations for the reduction of exhaust costs in ion implant tools and gas cabinets. (PDF)
Dec. 12 Host:  Anthony Muscat, University of Arizona
Presentation guest:  Uzo Okoroanyanwu, Lithography Engineer, AMD (currently conducting research at IMEC)
Topic:  "Resist Technology for the Post-157nm Lithography Era: Issues and Perspectives"
Abstract:  Fabrication of 35nm and smaller design rules in the post-157nm lithography era will present significant materials and process challenges for conventional resist technology. Image resolution achievable at these design rules using chemically amplified resist systems that have served the semiconductor industry remarkably well for over 25 years will be limited by acid diffusion and image spreading upon post-exposure bake.  Further, at this length scale, resist film thickness mandated by absorption considerations, are highly interfacial and are susceptible to spontaneous thin film instabilities due to London-van-der-Waals interactions. Properties such as glass transition temperature, Young’s modulus, polymer chain mobility, solvent absorption, acid transport, and deprotection kinetics of the confined resist polymer can deviate from bulk values. In particular, the glass transition temperature (Tg) may be depressed or elevated by as much as 40 °C relative to the bulk values, depending upon the film thickness and the chemical nature of the solid substrate upon which the film is deposited. This may have consequences on the viscoelastic response of the film during subsequent thermal annealing. Other practical consequences of changes in the thermophysical properties of the film include significant changes in dissolution, environmental sensitivity, and etching characteristics, as well as mechanical creep behavior, and adhesion of the resist.
Promising new, emerging, low-cost and environmentally friendly nanofabrication techniques exist for overcoming some of the limitations of conventional resist technology. Prominent among these techniques are nanoimprinting and molecular self-assembly. Although not quite matured at this time, some of these techniques have demonstrated sub-10 nm feature resolution with reasonable throughput, and good uniformity over a large area. These techniques are not entirely without problems.  
The level of accuracy and precision needed to fabricate 35nm and smaller devices requires the integration of the best practices of the conventional and emerging resist technologies. Ideas for implementing this integration along with the issues surrounding the two competing resist technology approaches will be discussed from both materials and process technology perspectives.
(Uzo Okoroanyanwu, Ph.D, Advanced Micro Devices, Strategic Lithography Technology Dept., Technology Research Group, Sunnyvale, CA 94088 USA  &  Currently on assignment at IMEC, Kapeldreef 75, B-3001, Leuven, Belgium) (PDF)
Dec. 19 Host:  Pierre Khuri-Yakub, Stanford University
Presentation by:  Utkan Demirci, Stanford University
Topic:  "Environmentally Benign Deposition of Photoresist and Low-k Dielectrics"
Abstract:  This research focuses on the minimization of wasted chemicals used in integrated circuits manufacturing; fluids such as photoresist, and low-k and high-k dielectrics.  A novel ejection technique is proposed to coat wafers with these expensive and hazardous fluids.  A new process for the fabrication of 2D ejector arrays has been developed using a wafer bonding technology for the ejector membrane formation.  First, fluid reservoirs are etched in a 400um thick silicon wafer. Then an SOI(Silicon on Insulator) wafer is bonded on top of the reservoirs. The thick portion of the SOI wafer is ground and etched in TMAH. The remaining thin silicon layer of SOI wafer forms the membranes after the SOI oxide is released. This method provides uniformity over the membranes. In the previous method we have used LPCVD silicon nitride film to form the membranes. The nitride properties, such as Young's modulus of residual stress, vary from run to run and even on the same wafer due to the non-uniform film deposition of LPCVD process. This results in non-uniform thin film properties and different resonance frequencies for the membranes of the same device. The new method eliminates these problems and provides excellent control over the thin film properties. Therefore, it is possible to build repeatable and predictable devices.  Results of ejectors built using this approach will be presented. (PDF)

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